Intel Arria 10 User Manual page 397

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Figure 189. Integer Mode phase aligned and external feedback
You must recalibrate the fPLL when you enable the phase alignment option.
1. Modify the fPLL IP to enable fPLL reconfiguration
• Under the Dynamic Reconfiguration Tab, turn ON Enable dynamic
reconfiguration.
2. Create logics in the core to perform following steps:
fPLL 1
fpll_t_iqtxrxclk
C
pm_iqtxrxclk_top[5:0]
refclk
pm_iqtxrxclk_top[3:0]
fbclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
fbclk
refclk
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
LCPLL 1
lc_t_iqtxrxclk
M
pm_iqtxrxclk_top[5:0]
refclk
pm_iqtxrxclk_top[3:0]
fbclk
Master
CGB 1
Note: (1) RX pin used as reference clock
6
4
Ch5
ch5_iqtxrxclk_2
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch5_iqtxrxclk_5
Ch4
ch4_iqtxrxclk_4
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch4_iqtxrxclk_4
Ch3
ch3_iqtxrxclk_0
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch3_iqtxrxclk_5
6
4
®
Intel Arria
pm_iqtxrx_t[5:0]
0 1 2 3 4 5
®
10 Transceiver PHY User Guide
397