Intel Arria 10 User Manual page 130

2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers
You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture,
and the reset controller before implementing the 10GBASE-R, 10GBASE-R with IEEE
1588v2, or 10GBASE-R with FEC Transceiver Configuration Rules.
You must design your own MAC and other layers in the FPGA to implement the
10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver
Configuration Rule using the Native PHY IP.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to
2. Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the
Transceiver configuration rule list located under Datapath Options,
depending on which protocol you are implementing.
3. Use the parameter values in the tables in
the 10GBASE-R Protocol
described in
for 10GBASE-R with IEEE 1588v2. You can then modify the settings to meet
your specific requirements.
4. Click Generate to generate the Native PHY IP core RTL file.
Figure 60. Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with
IEEE 1588v2, and 10GBASE-R with FEC
Generating the IP core creates signals and ports based on your parameter settings.
tx_serial_clk0 (from TX PLL)
5. Instantiate and configure your PLL.
® ®
Intel Arria 10 Transceiver PHY User Guide
130
Select and Instantiate the PHY IP Core
as a starting point. Or, you can use the protocol presets
Transceiver Native PHY
Nios Hard
tx_cal_busy
Calibration IP
rx_cal_busy
tx_serial_data
Clock
Generation
Block
rx_serial_data
rx_cdr_refclk0
CDR
rx_is_lockedtodata
rx_is_lockedtoref
Notes:
1. For 10GBASE-R with 1588 configurations, this signal is user-controlled.
2. For 10GBASE-R with 1588 configurations, this signal is connected from the output of TX FIFO in the FPGA fabric.
2. Implementing Protocols in Arria 10 Transceivers
on page 33 for more details.
Transceiver Native PHY Parameters for
Presets. Select 10GBASE-R Register Mode
Arria 10 Transceiver Native PHY
TX PMA TX Enhanced PCS
tx_parallel_data[127:0]
Serializer
RX PMA RX Enhanced PCS
Deserializer
rx_parallel_data[127:0]
UG-01143 | 2018.06.15
reconfig_reset
Reconfiguration
reconfig_clk
Registers
reconfig_avmm
tx_digitalreset
tx_control[17:0] xgmii_tx_c[7:0] (2)
xgmii_tx_d[63:0] (2)
tx_coreclkin xgmii_tx_clk
tx_clkout
tx_enh_data_valid 1'b1 (1)
tx_fifo_flags
tx_analogreset
rx_analogreset
rx_digitalreset
rx_clkout
rx_coreclkin
xgmii_rx_clk
rx_enh_blk_lock
rx_enh_highber
rx_fifo_flags
rx_control[19:0]