Intel Arria 10 User Manual page 201

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Definition: Device Support Level
Intel FPGA IP cores provide the following support for Intel FPGA device families:
• Preliminary support—Intel verifies the IP core with preliminary timing models for
this device family. The IP core meets all functional requirements, but might still be
undergoing timing analysis for the device family. This IP core can be used in
production designs with caution.
• Final support—Intel verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family. This IP core is ready to be used in production designs.
2.6.5.1.4. Resource Utilization
The following estimates are obtained by compiling the PHY IP core with the Intel
Quartus Prime software.
Table 153. Resource Utilization
Device
Arria 10
2.6.5.2. Using the IP Core
The Intel FPGA IP Library is installed as part of the Intel Quartus Prime installation
process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet IP core from the
library and parameterize it using the IP parameter editor.
2.6.5.2.1. Parameter Settings
You customize the PHY IP core by specifying the parameters in the parameter editor in
the Intel Quartus Prime software. The parameter editor enables only the parameters
that are applicable to the selected speed.
Table 154. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters
Name
Speed
Enable IEEE 1588 Precision
Time Protocol
Connect to MGBASE-T PHY
Speed
1G/2.5G
1G/2.5G with IEEE
1588v2 enabled
1G/2.5G/5G/10G
1G/2.5G/5G/10G
(USXGMII)
Value
2.5G
1G/2.5G
1G/2.5G/5G/10G
On, Off
On, Off
ALMs ALUTs
550 750
1200 1850
1150 1500
650 800
The operating speed of the PHY.
Select this parameter for the PHY to provide latency
information to the MAC. The MAC requires this
information if it enables the IEEE 1588v2 feature.
This parameter is enabled only for 2.5G and 1G/2.5G.
Select this option when the external PHY is MGBASE-T
compatible.
This parameter is enabled for 2.5G, 1G/2.5G, and 1G/
2.5G/10G (MGBASE-T) modes.
Intel
Logic Registers Memory Block
1200 2 (M20K)
2550 2 (M20K)
2550 6 (M20K)
1500 3 (M20K)
Description
continued...
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Arria 10 Transceiver PHY User Guide
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