Intel Arria 10 User Manual page 242

Figure 103. Use ATX PLL or fPLL for Gen1/Gen2 x8 Mode
Use Any
One PLL
® ®
Intel Arria 10 Transceiver PHY User Guide
242
Master
CGB
Connections Done
via X1 Network
fPLL1
Master
CGB
ATX PLL1
Master
CGB
Notes:
1. Figure shown is just one possible combination for the PCIe Gen1/Gen2 x8 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.
4. Gen1/Gen2 x8 mode uses the ATX PLL or fPLL only.
5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.
6. In this case the Master PCS channel is logical channel 4 (Ch 1 in the top bank).
2. Implementing Protocols in Arria 10 Transceivers
6 6 6
6
6
6
6
UG-01143 | 2018.06.15
Ch 5
CGB
CDR
Ch 4
CGB
CDR
Ch 3
CGB
CDR
Transceiver
bank
Ch 2
CGB
CDR
Ch 1
CGB
CDR
Ch 0
CGB
CDR
Ch 5
CGB
CDR
Transceiver
bank
Ch 4
CGB
CDR