Intel Arria 10 User Manual page 194

Addr Bit R/W
12 RO
14 RO
15 RO
0x496 0 R
1 R
0x4A2 15: RW
0
0x4A3 4:0 RW
0x4A4 0 RW
1 RW
3:2 RW
4 RW
2.6.4.7.5. PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data
interface, and provide status information.
® ®
Intel Arria 10 Transceiver PHY User Guide
194
Name
COPPER_DUPLEX_STATUS
ACK
COPPER_LINK_STATUS
LINK_PARTNER_AUTO_NEGOTIATIO
N_ABLE
PAGE_RECEIVE
Link timer[15:0]
Link timer[20:16]
SGMII_ENA
USE_SGMII_AN
SGMII_SPEED
SGMII half-duplex
2. Implementing Protocols in Arria 10 Transceivers
Description
Link partner capability:
• 1: copper interface is capable of full-duplex
operation
• 0: copper interface is capable of half-duplex
operation
Note: The PHY IP Core does not support half duplex
operation because it is not supported in SGMII
mode of the 1G/10G PHY IP core.
Link partner acknowledge. Value as specified in IEEE
802.3z standard.
Link partner status:
• 1: copper interface link is up
• 0: copper interface link is down
Set to 1, indicates that the link partner supports AN.
The default value is 0.
A value of 1 indicates that a new page has been
received with new partner ability available in the
register partner ability. The default value is 0 when
the system management agent performs a read
access.
Low-order 16 bits of the 21-bit auto-negotiation link
timer. Each timer step corresponds to 8 ns (assuming
a 125 MHz clock). The total timer corresponds to 16
ms. The reset value sets the timer to 10 ms for
hardware mode and 10 us for simulation mode.
High-order 5 bits of the 21-bit auto-negotiation link
timer.
Determines the PCS function operating mode. Setting
this bit to 1b'1 enables SGMII mode. Setting this bit
to 1b'0 enables 1000BASE-X gigabit mode.
In SGMII mode, setting this bit to 1b'1 configures the
PCS with the link partner abilities advertised during
auto-negotiation. If this bit is set to 1b'0, the PCS
function should be configured with the
and bits.
SGMII_DUPLEX
SGMII speed. When the PCS operates in SGMII mode
( ) and is not programmed for
SGMII_ENA = 1
automatic configuration (
USE_SGMII_AN = 0
following encodings specify the speed :
• 2'b00: 10 Mbps
• 2'b01: 100 Mbps
• 2'b10: Gigabit
• 2'b11: Reserved
These bits are not used when
.
USE_SGMII_AN = 1
When set to 1, enables half-duplex mode for 10/100
Mbps speed. This bit is ignored when
or = 1. These bits are only valid when
USE_SGMII_AN
you enable the SGMII mode only and not the
clause-37 auto-negotiation mode.
UG-01143 | 2018.06.15
SGMII_SPEED
), the
or
SGMII_ENA = 0
= 0
SGMII_ENA