Intel Arria 10 User Manual page 57

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Parameter
TX FIFO partially
empty threshold
Enable tx_enh_fifo_full
port
Enable
tx_enh_fifo_pfull port
Enable
tx_enh_fifo_empty
port
Enable
tx_enh_fifo_pempty
port
Table 19. Enhanced PCS RX FIFO Parameters
Parameter
RX FIFO Mode
RX FIFO partially full
threshold
RX FIFO partially
empty threshold
Enable RX FIFO
alignment word
deletion (Interlaken)
Range
2, 3, 4, 5 Specifies the partially empty threshold for the Enhanced PCS TX
FIFO. Enter the value at which you want the TX FIFO to flag a
partially empty status.
On / Off Enables the tx_enh_fifo_full port. This signal indicates when the
TX FIFO is full. This signal is synchronous to
On / Off Enables the tx_enh_fifo_pfull port. This signal indicates when
the TX FIFO reaches the specified partially full threshold. This
signal is synchronous to
On / Off Enables the tx_enh_fifo_empty port. This signal indicates when
the TX FIFO is empty. This signal is synchronous to
tx_coreclkin
On / Off Enables the tx_enh_fifo_pempty port. This signal indicates when
the TX FIFO reaches the specified partially empty threshold. This
signal is synchronous to
Range
Phase-Compensation Specifies one of the following modes for Enhanced PCS RX FIFO:
Register •
Interlaken
10GBASE-R
Basic •
•
•
•
Note: The flags are for Interlaken and Basic modes only. They
18-29 Specifies the partially full threshold for the Enhanced PCS RX
FIFO. The default value is 23.
2-10 Specifies the partially empty threshold for the Enhanced PCS RX
FIFO. The default value is 2.
On / Off When you turn on this option, all alignment words (sync words),
including the first sync word, are removed after frame
synchronization is achieved. If you enable this option, you must
also enable control word deletion.
Description
tx_coreclkin
.
tx_coreclkin
Description
Phase Compensation: This mode compensates for the clock
phase difference between the read clocks
and the write clock
tx_clkout
Register : The RX FIFO is bypassed. The
,
rx_parallel_data rx_control
are registered at the FIFO output. The
rx_enh_data_valid
FIFO's read clock
rx_coreclkin
are tied together.
Interlaken: Select this mode for the Interlaken protocol. To
implement the deskew process, you must implement an FSM
that controls the FIFO operation based on FIFO flags. In this
mode the FIFO acts as an elastic buffer.
10GBASE-R: In this mode, data passes through the FIFO
after block lock is achieved. OS (Ordered Sets) are deleted and
Idles are inserted to compensate for the clock difference
between the RX PMA clock and the fabric clock of +/- 100 ppm
for a maximum packet length of 64000 bytes.
Basic: In this mode, the RX FIFO acts as an elastic buffer. This
mode allows driving write and read side of FIFO with different
clock frequencies.
tx_coreclkin
have a minimum frequency of the lane data rate divided by
66. The frequency range for
tx_coreclkin
is (data rate/32) - (data rate/66). The
rx_coreclkin
gearbox data valid flag controls the FIFO read enable. You can
monitor the
rx_enh_fifo_pfull
flags to determine whether or not to read from the FIFO. For
additional details refer to Enhanced PCS FIFO Operation
page 297.
should be ignored in all other cases.
®
Intel Arria
.
tx_coreclkin
.
.
or
rx_coreclkin
.
rx_clkout
, and
and write clock
rx_clkout
or must
rx_coreclkin
or
and
rx_enh_fifo_empty
on
continued...
®
10 Transceiver PHY User Guide
57