Intel Arria 10 User Manual page 187

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Word Bit R/W
Addr
15 RW
16 RW
17 RW
0x4D0 22 RW
28:24 RW
31:29 RW
0x4D1 0 RW
4 RW
8 RW
0x4D2 0 RO
1 RO
2 RO
Name
The default value is 010.
When set to 1, PMA values (VOD, pre-tap, post-tap) are not
disable Initialize
initialized upon entry into the
PMA on
happens when
max_wait_timeout
training_failure
University of New Hampshire (UNH) testing. When set to 0, PMA
values are initialized upon entry into
Refer to Figure 72-5 of IEEE 802.3ap-2007 for more details.
When set to 1, overrides the link partner's equalization
Ovride LP Coef
coefficients; software changes the update commands sent to the
enable
link partner TX equalizer coefficients. When set to 0, uses the Link
Training logic to determine the link partner coefficients. Used with
0x4D1 bit-4 and 0x4D4 bits[7:0].
When set to 1, overrides the local device equalization coefficients
Ovride Local RX
generation protocol. When set, the software changes the local TX
Coef enable
equalizer coefficients. When set to 0, uses the update command
received from the link partner to determine local device
coefficients. Used with 0x4D1 bit-8 and 0x4D4 bits[23:16]. The
default value is 1.
Reserved. Default = 000
adp_ctle_mode
Reserved
Manual ctle
Reserved
max_post_step[2:0]
When set to 1, resets the 10GBASE-KR start-up protocol. When
Restart Link
set to 0, continues normal operation. This bit self clears. For more
training
information, refer to the state variable mr_restart_training as
defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control
register bit (1.150.0) IEEE 802.3ap-2007.
When set to 1, there are new link partner coefficients available to
Updated TX Coef new
send. The LT logic starts sending the new values set in 0x4D4
bits[7:0] to the remote device. When set to 0, continues normal
operation. This bit self clears. Must enable this override in 0x4D0
bit 16.
When set to 1, new local device coefficients are available. The LT
Updated RX coef new
logic changes the local TX equalizer coefficients as specified in
0x4D4 bits[23:16]. When set to 0, continues normal operation.
This bit self clears. Must enable the override in 0x4D0 bit17.
When set to 1, the receiver is trained and is ready to receive
Link Trained -
data. When set to 0, receiver training is in progress. For more
Receiver status
information, refer to the state variable rx_trained as defined in
Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control register bit
10GBASE_KR PMD status register bit (1.151.0) of IEEE
802.3ap-2007.
When set to 1, the training frame delineation has been detected.
Link Training Frame
When set to 0, the training frame delineation has not been
lock
detected. For more information, refer to the state variable
frame_lock as defined in Clause 72.6.10.3.1 and 10GBASE_KR
PMD status register bit 10GBASE_KR PMD status register bit
(1.151.1) of IEEE 802.3ap-2007.
When set to 1, the start-up protocol is in progress. When set to 0,
Link Training
start-up protocol has completed. For more information, refer to
Start-up protocol
the state training as defined in Clause 72.6.10.3.1 and
status
10GBASE_KR PMD status register bit (1.151.2) of IEEE
802.3ap-2007.
Description
Training_Failure
, which sets
max_wait_timer_done
= true (reg 0x4D2 bit 3). Used for
Training_Failure
® ®
Intel Arria 10 Transceiver PHY User Guide
state. This
state.
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