Intel Arria 10 User Manual page 526

Example 2:
Switching from
both fPLL refclk selection MUX_0 and MUX_1:
1. Modify MUX_0 value:
• Read from 0x11A [7:0]
• Write the value read from 0x11A [7:0] to 0x114 [7:0]
2. Modify MUX_1 value:
• Read from 0x120 [7:0]
• Write the value read from 0x120 [7:0] to 0x11C [7:0]
Related Information
Steps to Perform Dynamic Reconfiguration
6.11.2.3. CDR and CMU Reference Clock Switching
You can use the reconfiguration interface to specify which reference clock source
drives the CDR and CMU PLL. The CDR and CMU support clocking by up to five
different reference clock sources.
Before initiating a reference clock switch, ensure that your CDR and CMU defines more
than one reference clock source. For the CDR, specify the parameter on the RX PMA
tab during the Native PHY IP parameterization. For the CMU, specify the Number of
PLL reference clocks under the PLL tab when parameterizing the CMU PLL.
The following table describes the addresses and bits for switching CDR and CMU
reference clock inputs. The number of exposed
pll_refclk
Use the CMU reconfiguration interface for switching the CMU reference clock.
Table 271. Register Map for Switching CDR Reference Clock Inputs
Native PHY Port
cdr_refclk0
cdr_refclk1
cdr_refclk2
® ®
Intel Arria 10 Transceiver PHY User Guide
526
6. Reconfiguration Interface and Dynamic Reconfiguration
to
pll_refclk2 pll_refclk3
(CMU) varies according to the number of reference clocks you specify.
Description
Represents logical
refclk0
Lookup register
x16A[7:0]
stores the mapping from logical
to the physical refclk.
refclk0
Represents logical
refclk1
Lookup register
x16B[7:0]
stores the mapping from logical
to the physical refclk.
refclk1
Represents logical
refclk2
Lookup register
x16C[7:0]
stores the mapping from logical
to the physical refclk.
refclk2
, you need to read-modify-write to
on page 516
rx_cdr_refclk
Address
0x16A (Lookup Register)
.
0x16B (Lookup Register)
.
0x16C (Lookup Register)
.
UG-01143 | 2018.06.15
(CDR) or
Bits
[7:0]
[7:0]
[7:0]
continued...