Intel Arria 10 User Manual page 525

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Transceiver fPLL Port
N/A
pll_refclk0
pll_refclk1
pll_refclk2
pll_refclk3
pll_refclk4
N/A
Specify the logical reference clock and respective address and bits of the replacement
clock when performing a reference clock switch. Follow this procedure to switch to the
selected reference clock:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Read from the lookup register for MUX 0 and save the required 8-bit pattern. For
example, switching to logical
0x11A.
3. Perform a read-modify-write to bits [7:0] at address 0x114 using the 8-bit value
obtained from the lookup register.
4. Read from the lookup register for MUX 1 and save the required 8-bit pattern. For
example, switching to logical
0x120.
5. Perform a read-modify-write to bits [7:0] at address 0x11C using the 8-bit value
obtained from the lookup register.
6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
Example 1:
Switching from
both fPLL refclk selection MUX_0 and MUX_1:
1. Modify MUX_0 value:
• Read from 0x118[7:0]
• Write the value from 0x118 [7:0] to 0x114 [7:0]
2. Modify MUX_1 value:
• Read from 0x11E [7:0]
• Write the value read from 0x11E [7:0] to 0x11C [7:0]
Description
fPLL refclk selection .
MUX_0
Represents logical for
refclk0
register stores the mapping from logical
x11D[7:0]
to the physical refclk for MUX_1.
refclk0
Represents logical for
refclk1
register stores the mapping from logical
x11E[7:0]
to the physical refclk for MUX_1.
refclk1
Represents logical for
refclk2
register stores the mapping from logical
x11F[7:0]
to the physical refclk for MUX_1.
refclk2
Represents logical for
refclk3
register stores the mapping from logical
x120[7:0]
to the physical refclk for MUX_1.
refclk3
Represents logical for
refclk4
register stores the mapping from logical
x121[7:0]
to the physical refclk for MUX_1.
refclk4
fPLL refclk selection .
MUX_1
refclk3
refclk3
to
pll_refclk0 pll_refclk1
0x114
0x11D (Lookup Register)
. Lookup
MUX_1
0x11E (Lookup Register)
. Lookup
MUX_1
. Lookup 0x11F (Lookup Register)
MUX_1
0x120 (Lookup Register)
. Lookup
MUX_1
0x121 (Lookup Register)
. Lookup
MUX_1
0x11C
requires use of bits[7:0] at lookup register
requires use of bits[7:0] at lookup register
, you need to read-modify-write to
®
Intel Arria
Address Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
®
10 Transceiver PHY User Guide
525