Intel Arria 10 User Manual page 22

Figure 13. Six-Channel GX Transceiver Bank Architecture
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
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Intel Arria 10 Transceiver PHY User Guide
22
Six-Channel GX Transceiver Bank
CH5
PMA
Channel PLL
Local CGB5
(CDR Only)
CH4
PMA
Channel PLL
Local CGB4
(CMU/CDR)
CH3
PMA
Channel PLL
Local CGB3
(CDR Only)
CH2
PMA
Channel PLL
Local CGB2
(CDR Only)
CH1
PMA
Channel PLL
Local CGB1
(CMU/CDR)
CH0
PMA
Channel PLL
Local CGB0
(CDR Only)
1. Arria
Clock
Distribution
Network
PCS
PCS
PCS
PCS
PCS
PCS
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10 Transceiver PHY Overview
UG-01143 | 2018.06.15
fPLL1
Master
CGB1
FPGA Core
ATX
Fabric
PLL1
fPLL0
Master
CGB0
ATX
PLL0