Intel Arria 10 User Manual page 166

2.6.4.2. 1G/10GbE PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the 1G/10GbE PHY IP core
in Arria 10 devices.
The following table shows the typical expected resource utilization for selected
configurations using the Quartus Prime software version 15.1. The numbers of ALMs
and logic registers are rounded up to the nearest 50.
Table 128. 1GbE/10GbE PHY Performance and Resource Utilization
Variant
1G/10GbE PHY with IEEE 1588 v2
1G/10GbE PHY
1G/10GbE PHY with FEC
2.6.4.3. 1G/10GbE PHY Functional Description
Figure 73. 1G/10GbE PHY Block Diagram
User PCS Reconfiguration
TX_GMII_DATA
XGMII_TX_CLK
TX_XGMII_DATA
TX_PMA_CLKOUT
RX_XGMII_DATA
XGMII_RX_CLK
RX_GMII_DATA
RX_PMA_CLKOUT
RX_DIV_CLKOUT
Standard and Enhanced PCS Datapaths
The Standard PCS and PMA inside the Native PHY are configured as the Gigabit
Ethernet PHY. The Enhanced PCS and PMA inside the Native PHY are configured as the
10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters
for more details.
® ®
Intel Arria 10 Transceiver PHY User Guide
166
ALMs
2650
1500
1500
Avalon-MM
MGMT_CLK
Sequencer
PCS Reconfiguration I/F
(Auto-Speed
Detect)
8 + 2
64 + 8
Auto-Negotiation
Clause 73
Link Training
Clause 72
40
64 + 8
8 + 2
GigE
PCS
Soft Logic Hard Logic Not Available
2. Implementing Protocols in Arria 10 Transceivers
ALUTs
3950 5100
2350 2850
2350 2850
PMA Reconfiguration I/F
Reconfiguration
Block
GigE
PCS
Native PHY
1588
FIFO
tx_pld_clk tx_pma_clk
66
Enhanced TX PCS
40
tx_pld_clk tx_pma_clk
1588
FIFO
rx_pld_clk rx_pma_clk
Enhanced RX PCS
rx_pld_clk rx_pma_clk
UG-01143 | 2018.06.15
Registers M20K
6
2
2
Registers
HSSI Reconfiguration Requests
40/32
Standard TX PCS
TX PMA
Standard RX PCS
40/32
RX PMA
Divide by 33/1/2