Intel Arria 10 User Manual page 361

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
before the feedback clock's falling edge. Conversely, the PFD generates a "Down"
signal when the feedback clock's falling edge occurs before the reference clock's falling
edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control
voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a
control voltage that drives the VCO frequency.
Voltage Controlled Oscillator
The fPLL has a ring oscillator based VCO. The VCO transforms the input control
voltage into an adjustable frequency clock.
VCO freq = 2 * M * Input reference clock/N. (N and M are the N counter and M
counter division factors.)
L Counter
The L counter divides the VCO's clock output. When the fPLL acts as a transmit PLL,
the output of the L counter drives the clock generation block (CGB) and the TX PMA
via the X1 clock lines.
M Counter
The M counter divides the VCO's clock output. The M counter can select any VCO
phase. The outputs of the M counter and N counter have same frequency. M counter
range is 8 to 127 in integer mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The delta sigma modulator is used in fractional mode. It modulates the M counter
divide value over time so that the PLL can perform fractional frequency synthesis.
In fractional mode, the M value is as follows:
M (integer) + K/2^32, where K is the fractional multiply factor (K) in the fPLL IP
Parameter Editor. The legal values of K are greater than 1% and less than 99% of the
full range of 2^32 and can only be manually entered in the fPLL IP Parameter Editor in
the Quartus Prime software.
The output frequencies can be exact when the fPLL is configured in fractional mode.
Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO
frequency, not all desired fractional values can be achieved exactly. The lock signal is
not available, when configured in fractional mode in the K-precision mode (K < 0.1 or
K > 0.9).
C Counter
The fPLL C counter division factors range from 1 to 512.
Dynamic Phase Shift
The dynamic phase shift block allows you to adjust the phase of the C counters in user
mode. In fractional mode, dynamic phase shift is only available for the C counters.
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Intel Arria 10 Transceiver PHY User Guide
361