Intel Arria 10 User Manual page 210

Signal Name
tx_digitalreset
rx_analogreset
rx_digitalreset
2.6.5.4.2. Operating Mode and Speed Signals
Table 159. Transceiver Mode and Operating Speed Signals
Signal Name
xcvr_mode
operating_speed
2.6.5.4.3. GMII Signals
The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz
respectively.
Table 160. GMII Signals
Signal Name
TX GMII signals—synchronous to
gmii16b_tx_d
gmii16b_tx_en
gmii16b_tx_err
® ®
Intel Arria 10 Transceiver PHY User Guide
210
Direction Width
Input 1
Input 1
Input 1
Direction Width
Input 2
Output 3
Direction Width
tx_clkout
Input 16
Input 2
Input 2
2. Implementing Protocols in Arria 10 Transceivers
Description
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the TX
path.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the receiver CDR.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the RX
path.
Description
Connect this signal to the reconfiguration block.
Use the values below to set the speed:
• 0x0 = 1G
• 0x1 = 2.5G
• 0x3 = 10G
Connect this signal to the MAC. This signal
provides the current operating speed of the PHY:
• 0x0 = 10G
• 0x1 = 1G
• 0x4 = 2.5G
• 0x5 = 5G
Description
TX data from the MAC. The MAC sends the lower
byte first followed by the upper byte.
When asserted, indicates the start of a new frame
from the MAC. Bit[0] corresponds to
[7:0]; bit[1] corresponds to
gmii16b_tx_d
[15:8].
gmii16b_tx_d
This signal remains asserted until the PHY receives
the last byte of the data frame.
When asserted, indicates an error. Bit[0]
corresponds to
gmii16b_tx_err
corresponds to
gmii16b_tx_err
The bits can be asserted at any time during a
frame transfer to indicate an error in the current
frame.
UG-01143 | 2018.06.15
[7:0]; bit[1]
[15:8].
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