Intel Arria 10 User Manual page 575

7. Calibration
UG-01143 | 2018.06.15
Figure 282. Power-up Calibration Sequence for Non-PCIe Hard IP (HIP) Channels
For applications not using PCIe Hard IP, the power-up calibration starts from Vreg calibration for all banks and
channels. Then, PreSICE calibration is done in the sequence as shown in the following figure.
For applications using both PCIe Hard IP and non-PCIe channels, the power-up
calibration sequence is:
1. Vreg calibration for all banks and channels.
2. Wait for PCIe reference clock toggle.
3. PCIe Hard IP 0 calibration (if used).
4. PCIe Hard IP 1 calibration (if used).
5. Calibration of all non-PCIe Hard IP channels in calibration sequence.
Bank 1
ATX PLL Calibration
After All ATX PLLs Calibrated
Bank 1
fPLL Calibration
After All fPLLs Calibrated
Bank 1
RX PMA and TX PMA Calibration
(1) CDR and CMU PLL calibration are part of RX
PMA calibration.
Bank ...
Bank 2
Bank ...
Bank 2
Bank ...
Bank 2
(1)
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Intel Arria 10 Transceiver PHY User Guide
575