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2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 102. Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode
fPLL1
ATX PLL1
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 x4 modes use the ATX PLL or fPLL only.
5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.
6.
In this case the Master PCS channel is logical channel 3 (physical channel 4).
XN
Network
6
6
Connections Done
via X1 Network
Master
6
CGB
6
Master
CGB
X6
Network
Ch 5
CGB
CDR
6
6
Ch 4
CGB
CDR
Ch 3
CGB
CDR
Ch 2
CGB
CDR
Ch 1
CGB
CDR
Ch 0
CGB
CDR
®
Intel
Arria
®
10 Transceiver PHY User Guide
241
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