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Figure 215. Transceiver PHY Reset Controller System Diagram
Status Signals
tx_ready
Reset Controller
clock
(user-coded
or Intel IP)
reset
Transmit
PLL
clk_usrpin
Note:
(1)
You can logical OR the pll_cal_busy and tx_cal_busy signals.
pll_tx_cal_busy connects to the controller's tx_cal_busy input port.
(2) The ports are inputs for user logic that implement Model 2. The ports can be used as status monitoring for Model 1 implementation.
.
®
®
Intel
Arria
10 Transceiver PHY User Guide
434
rx_ready
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
tx_analogreset_ack
(2)
(2)
rx_analogreset_ack
pll_tx_cal_busy
tx_cal_busy (1)
pll_cal_busy (1)
Transceiver Reset Sequencer Inferred Block
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Transceiver PHY Instance
Transmitter
PCS
Receiver
PCS
Transmitter
PMA
Receiver
PMA
Optional
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