Intel Arria 10 User Manual page 131

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
6. Create a transceiver reset controller. You can use your own reset controller or use
the Arria 10 Transceiver Native PHY Reset Controller IP.
7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
Figure 61. Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
through XGMII
Figure 62. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
through XGMII
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Enhanced PCS Architecture
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture
For more information about PMA architecture
• Using PLLs and Clock Networks
For more information about implementing PLLs and clocks
• PLLs
PLL architecture and implementation details
• Resetting Transceiver Channels
Reset controller general information and implementation details
• Enhanced PCS Ports
For detailed information about the available ports in the 10GBASE-R 1588
protocol.
To MAC/RS
Interface
64d + 8c
To MAC/RS
Interface
FIFO in the
64d + 8c
FPGA core
for TX
FIFO in the
FPGA core
64d + 8c
for RX
on page 447
on page 349
on page 76
Reset
PLL IP
Controller
Arria 10 Transceiver
Native PHY
PLL IP
Arria 10 Transceiver
Native PHY
on page 461
on page 398
on page 416
®
Intel Arria
Medium
Reset
Controller
Medium
®
10 Transceiver PHY User Guide
131