Intel Arria 10 User Manual page 357

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Parameter
Generate SystemVerilog package
file
Generate C header file
Enable multiple reconfiguration
profiles
Enable embedded reconfiguration
streamer
Generate reduced reconfiguration
files
Number of reconfiguration profiles
Store current configuration to
profile
Generate MIF (Memory Initialize
File)
Table 232. ATX PLL—Generation Options
Parameter
Generate parameter
documentation file
Table 233. ATX PLL IP Core Ports
Port
pll_powerdown
pll_refclk0
pll_refclk1
pll_refclk2
pll_refclk3
pll_refclk4
tx_serial_clk
Range
On/Off Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
On/Off Generates a C header file containing all relevant parameters
used by the PLL.
On/Off Enables multiple configuration profiles to be stored.
On/Off Enables embedded reconfiguration streamer which
automates the dynamic reconfiguration process between
multiple predefined configuration profiles.
On/Off When enabled, the IP generates reconfiguration report files
containing only the setting differences between the multiple
reconfiguration profiles
1 to 8 Specifies the number of reconfiguration profiles
0 to 7 Specifies which configuration profile to modify (store, load,
clear or refresh) when clicking the corresponding action
button.
On/Off Generates a MIF file which contains the current
configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
Range
On/Off Generates a .csv file which contains descriptions of ATX PLL
IP core parameters and values.
Direction Clock Domain
Input Asynchronous
Input N/A
Input N/A
Input N/A
Input N/A
Input N/A
Output N/A
Description
Description
Description
Resets the PLL when asserted high.
Needs to be connected to a
dynamically controlled signal (the
Transceiver PHY Reset Controller
pll_powerdown output if using this
Intel FPGA IP).
Reference clock input port 0.
There are a total of five reference clock
input ports. The number of reference
clock ports available depends on the
Number of PLL reference clocks
parameter.
Reference clock input port 1.
Reference clock input port 2.
Reference clock input port 3.
Reference clock input port 4.
High speed serial clock output port for
GX channels. Represents the x1 clock
network.
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Intel Arria 10 Transceiver PHY User Guide
357