Intel Arria 10 User Manual page 24

Figure 15. GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
The transceiver channels perform all the required PHY layer functions between the
FPGA fabric and the physical medium. The high speed clock required by the
transceiver channels is generated by the transceiver PLLs. The master and local clock
generation blocks (CGBs) provide the necessary high speed serial and low speed
parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.
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Intel Arria 10 Transceiver PHY User Guide
24
Six-Channel GT
Transceiver Banks GXBL1E and GXBL1H
CH5
PMA
PCS
Channel PLL
Local CGB5
(CDR Only)
CH4
PMA
PCS
Channel PLL
Local CGB4
(CMU/CDR)
CH3
PMA
PCS
Channel PLL
Local CGB3
(CDR Only)
CH2
PMA
PCS
Channel PLL
(CDR Only) Local CGB2
CH1
PMA
PCS
Channel PLL
Local CGB1
(CMU/CDR)
CH0
PMA
PCS
Channel PLL
Local CGB0
(CDR Only)
Legend
GT/GX Channel GX Channel
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1. Arria 10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Clock
Distribution
Network
fPLL1
Master
CGB1
FPGA Core
ATX
PLL1
fPLL0
Master
CGB0
ATX
PLL0
Fabric