Intel Arria 10 User Manual page 63

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 30. Standard PCS Parameters
Note:
Parameter
Standard PCS/PMA
interface width
FPGA fabric/Standard
TX PCS interface width
FPGA fabric/Standard
RX PCS interface width
Enable Standard PCS
low latency mode
Table 31. Standard PCS FIFO Parameters
Parameter
TX FIFO mode
RX FIFO mode
Enable
tx_std_pcfifo_full port
Enable
tx_std_pcfifo_empty
port
Enable
rx_std_pcfifo_full port
Enable
rx_std_pcfifo_empty
port
For detailed descriptions of the optional ports that you can enable or disable, refer to the
Standard PCS Ports on page 86 section.
Range
8, 10, 16, 20 Specifies the data interface width between the Standard PCS and
the transceiver PMA.
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard TX PCS datapath.
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard RX PCS datapath.
On / Off Enables the low latency path for the Standard PCS. Some of the
functional blocks within the Standard PCS are bypassed to provide
the lowest latency. You cannot turn on this parameter while using
the Basic/Custom w/Rate Match (Standard PCS) specified for
Transceiver configuration rules.
Range
low_latency Specifies the Standard PCS TX FIFO mode. The following modes
are available:
register_fifo
•
fast_register
•
•
low_latency The following modes are available:
register_fifo •
•
On / Off
Enables the
when the standard TX phase compensation FIFO is full. This signal
is synchronous with
On / Off
Enables the
when the standard TX phase compensation FIFO is empty. This
signal is synchronous with
On / Off
Enables the
when the standard RX phase compensation FIFO is full. This signal
is synchronous with
On / Off
Enables the
when the standard RX phase compensation FIFO is empty. This
signal is synchronous with
Description
Description
low_latency: This mode adds 2-3 cycles of latency to the TX
datapath.
register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI.
fast_register: This mode allows a higher maximum frequency
(f ) between the FPGA fabric and the TX PCS at the expense
MAX
of higher latency.
low_latency: This mode adds 2-3 cycles of latency to the RX
datapath.
register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI or
1588.
tx_std_pcfifo_full
tx_coreclkin
tx_std_pcfifo_empty
tx_coreclkin
rx_std_pcfifo_full
rx_coreclkin
rx_std_pcfifo_empty
rx_coreclkin
®
Intel Arria
port. This signal indicates
.
port. This signal indicates
.
port. This signal indicates
.
port. This signal indicates
.
®
10 Transceiver PHY User Guide
63