Using Pseudo Random Pattern Mode - Intel Arria 10 User Manual

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15

6.16.2. Using Pseudo Random Pattern Mode

You can use the Arria 10 Pseudo Random Pattern (PRP) generator and verifier in the
scrambler and descrambler to generate random data pattern and seed that the
scrambler can use. PRP mode is a test mode of the scrambler. Two seeds are available
to seed the scrambler: all 0s or two local fault-ordered sets. The seed is used in the
scrambler to produce the pattern. The
the scrambler will scramble. PRP is only available when the scrambler is enabled. The
PRP verifier shares the
read out from the corresponding registers.
6.16.2.1. Enabling Pseudo Random Pattern Mode
You must perform a sequence of read-modify-writes to the reconfiguration interface to
enable the Pseudo Random Pattern. The read-modify-writes are required to addresses
0x082, 0x097, and 0x0AC. To enable the Pseudo Random Pattern, complete the
following steps:
1. Perform the necessary steps from steps 1 to 7 in Steps to Perform Dynamic
Reconfiguration.
2. Perform a read-modify-write to address 0x082 according to
559.
3. Perform a read-modify-write to address 0x097 according to
559.
4. Perform a read-modify-write to address 0x0AC according to
559.
5. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic
Reconfiguration.
To disable the PRP verifier, write the original values back to the read-modify-write
addresses listed above.
Table 295. Register Map for Pseudo Random Pattern Mode
Reconfiguration Reconfiguration
Address (HEX)
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
rx_prbs_err
Attribute Name
Bit
[7:0] r_tx_seed_a[7:0]
[7:0] r_tx_seed_a[15:8]
[7:0] r_tx_seed_a[23:16]
[7:0] r_tx_seed_a[31:24]
[7:0] r_tx_seed_a[39:32]
[7:0] r_tx_seed_a[47:40]
[7:0] r_tx_seed_a[55:48]
[1:0] r_tx_seed_a[57:56]
r_tx_data_pat_sel
error signal with PRBS. The error count can be
Bit Encoding
® ®
Intel Arria
is the data pattern that
Table 295 on page
Table 295 on page
Table 295 on page
Description
Seed A value
bit[7:0]
Seed A value
bit[15:8]
Seed A value
bit[23:16]
Seed A value
bit[31:24]
Seed A value
bit[39:32]
Seed A value
bit[47:40]
Seed A value
bit[55:48]
Seed A value
bit[57:56]
continued...
10 Transceiver PHY User Guide
559