Intel Arria 10 User Manual page 370

Transceiver phy
Hide thumbs Also See for Arria 10:
Table of Contents

Advertisement

3.1.4.1. Instantiating CMU PLL IP Core
The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in
hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.
1. Open the Quartus Prime software.
2. Click Tools
3. In IP Catalog, under Library
CMU PLL and click Add.
4. In the New IP Instance Dialog Box, provide the IP instance name.
5. Select Arria 10 device family.
6. Select the appropriate device and click OK.
The CMU PLL IP core Parameter Editor window opens.
3.1.4.2. CMU PLL IP Core
Table 240.
CMU PLL Parameters and Settings
Parameters
Message level for rule violations
Bandwidth
Number of PLL reference clocks
Selected reference clock source
TX PLL Protocol mode
PLL reference clock frequency
PLL output frequency
Multiply factor (M-Counter)
Divide factor (N-Counter)
Divide factor (L-Counter)
®
®
Intel
Arria
10 Transceiver PHY User Guide
370
IP Catalog.
Transceiver PLL , select Arria 10 Transceiver
Range
Error
Specifies the messaging level to use for parameter rule
violations.
Warning
Low
Specifies the VCO bandwidth.
Medium
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
High
1 to 5
Specifies the number of input reference clocks for the CMU
PLL.
You can use this parameter for data rate reconfiguration.
0 to 4
Specifies the initially selected reference clock input to the
CMU PLL.
BASIC
This parameter governs the rules for correct protocol
specific settings. Certain features of the PLL are only
PCIe
available for specific protocol configuration rules. This
parameter is not a preset .
You must set all the other parameters for your protocol.
Refer to the GUI
Selects the input reference clock frequency for the PLL.
Refer to the GUI
Specify the target output frequency for the PLL.
Read only
Displays the M-multiplier value.
Read only
Displays the N-counter value.
Read only
Displays the L-counter value.
3. PLLs and Clock Networks
Description
Error - Causes all rule violations to prevent IP
generation.
Warning - Displays all rule violations as warnings and
allows IP generation in spite of violations.
UG-01143 | 2018.06.15

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents