Intel Arria 10 User Manual page 53

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Parameter
Enable
tx_pma_iqtxrx_clkout port
Enable tx_pma_elecidle
port
Enable tx_pma_qpipullup
port (QPI)
Enable tx_pma_qpipulldn
port (QPI)
Enable tx_pma_txdetectrx
port (QPI)
Enable tx_pma_rxfound
port (QPI)
Enable rx_seriallpbken port
Table 14. RX CDR Options
Parameter
Number of CDR
reference clocks
Selected CDR
reference clock
Selected CDR
reference clock
frequency
PPM detector
threshold
Table 15. Equalization
Parameters
CTLE adaptation mode
(25)
The default value is Disabled.
Value
On/Off
Enables the optional
clock can be used to cascade the TX PMA output clock to the input
of a PLL.
On/Off
Enables the
the transmitter is forced into an electrical idle condition. This port
has no effect when the transceiver is configured for PCI Express.
On/Off
Enables the
only for Quick Path Interconnect (QPI) applications.
On/Off
Enables the
only for QPI applications.
On/Off
Enables the
detect block in the TX PMA detects the presence of a receiver at
the other end of the channel. After receiving a
tx_pma_txdetectrx
the detection process. Use this port only in QPI applications.
On/Off
Enables the
detect block in TX PMA detects the presence of a receiver at the
other end by using the
tx_pma_rxfound
operation. Use this port only in QPI applications.
On/Off
Enables the optional
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
Value
1 - 5 Specifies the number of CDR reference clocks. Up to 5 sources are
possible.
The default value is 1.
Use this feature when you want to dynamically re-configure CDR
reference clock source.
0 to <number of CDR Specifies the initial CDR reference clock. This parameter
reference clocks> -1 determines the available CDR references used.
The default value is 0.
< data rate dependent > Specifies the CDR reference clock frequency. This value depends
on the data rate specified.
100 Specifies the PPM threshold for the CDR. If the PPM between the
incoming serial data and the CDR reference clock, exceeds this
300
threshold value, the CDR loses lock.
500
The default value is 1000.
1000
Value
Manual Specifies the Continuous Time Linear Equalization (CTLE)
operation mode.
Description
tx_pma_iqtxrx_clkout
port. When you assert this port,
tx_pma_elecidle
control input port. Use this port
tx_pma_qpipullup
control input port. Use this port
tx_pma_qpipulldn
control input port. The receiver
tx_pma_txdetectrx
request the receiver detect block initiates
status output port. The receiver
tx_pma_rxfound
tx_pma_txdetectrx
port reports the status of the detection
control input port. The
rx_seriallpbken
Description
Description
® ®
Intel Arria 10 Transceiver PHY User Guide
output clock. This
input. The
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