Intel Arria 10 User Manual page 167

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Sequencer
The Sequencer controls the start-up sequence of the PHY IP, including reset and
power-on. It selects which PCS (1G or 10G) and PMA interface is active. The
Sequencer interfaces to the reconfiguration block to request a change from one data
rate to the other data rate.
GigE PCS
The GigE PCS includes the GMII interface and Clause 37 auto negotiation and SGMII
functionality.
Soft Enhanced PCS FIFO for IEEE 1588v2
In IEEE 1588v2 mode, the enhanced PCS FIFOs for both TX and RX are constructed in
soft IP to include the latency information via the latency adjustment ports. For more
information about the required latency information in the MAC as part of the Precision
Time Protocol implementation, refer to the 10-Gbps Ethernet MAC IP Function User
Guide.
Reconfiguration Block
The reconfiguration logic performs the Avalon-MM writes to the PHY for both PCS and
PMA reconfiguration. The following figure shows the details of the reconfiguration
blocks. The Avalon-MM master accepts requests from the PMA or PCS controller. It
performs the Read-Modify-Write or Write commands using the Avalon-MM interface.
The PCS controller receives data rate change requests from the Sequencer and
translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Figure 74. Reconfiguration Block Details
The 1G/10GbE PHY IP core is very flexible. For example, you can configure it with or without IEEE 1588v2, and
with or without FEC in the enhanced PCS datapath.
MGMT_CLK
(2)
PCS
Reconfiguration
Interface
PMA
Reconfiguration
Interface
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
rcfg_data
rcfg_data
rcfg_data
PCS
Controller
PMA Controller
Avalon-MM Bus
TX EQ Controller
DFE Controller
Avalon-MM reconfig_busy Signal
CTLE Controller
rcfg_data
Avalon-MM Bus
(1)
Avalon-MM Bus
Avalon-MM
Decoder
® ®
Intel Arria 10 Transceiver PHY User Guide
HSSI
Reconfiguration
Requests
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