Intel Arria 10 User Manual page 61

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 26. Interlaken Disparity Generator and Checker Parameters
Parameter
Enable Interlaken TX
disparity generator
Enable Interlaken RX
disparity checker
Enable Interlaken TX
random disparity bit
Table 27. Block Synchronizer Parameters
Parameter
Enable RX block
synchronizer
Enable
rx_enh_blk_lock port
Table 28. Gearbox Parameters
Parameter
Enable TX data bitslip
Enable TX data polarity
inversion
Enable RX data bitslip
Enable RX data
polarity inversion
Enable tx_enh_bitslip
port
Enable rx_bitslip port
Note: If a design is slipping more bits than the PCS/PMA width, the Enhanced RX PCS FIFO
could overflow. To clear the overflow, assert
Range
On / Off When you turn on this option, the Enhanced PCS enables the
disparity generator. This option is available for the Interlaken
protocol.
On / Off When you turn on this option, the Enhanced PCS enables the
disparity checker. This option is available for the Interlaken
protocol.
On / Off Enables the Interlaken random disparity bit. When enabled, a
random number is used as disparity bit which saves one cycle of
latency.
Range
On / Off When you turn on this option, the Enhanced PCS enables the RX
block synchronizer. This options is available for the Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.
On / Off
Enables the
synchronizer, this signal is asserted to indicate that the block
delineation has been achieved.
Range
On / Off When you turn on this option, the TX gearbox operates in bitslip
mode. The tx_enh_bitslip port controls number of bits which TX
parallel data slips before going to the PMA.
On / Off When you turn on this option, the polarity of TX data is inverted.
This allows you to correct incorrect placement and routing on the
PCB.
On / Off When you turn on this option, the Enhanced PCS RX block
synchronizer operates in bitslip mode. When enabled, the
rx_bitslip port is asserted on the rising edge to ensure that RX
parallel data from the PMA slips by one bit before passing to the
PCS.
On / Off When you turn on this option, the polarity of the RX data is
inverted. This allows you to correct incorrect placement and
routing on the PCB.
On / Off Enables the tx_enh_bitslip port. When TX bit slip is enabled,
this signal controls the number of bits which TX parallel data slips
before going to the PMA.
On / Off Enables the rx_bitslip port. When RX bit slip is enabled, the
rx_bitslip
RX parallel data from the PMA slips by one bit before passing to
the PCS. This port is shared between Standard PCS and Enhanced
PCS.
Description
Description
port. When you enable the block
rx_enh_blk_lock
Description
signal is asserted on the rising edge to ensure that
.
rx_digitalreset
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Intel Arria 10 Transceiver PHY User Guide
61