Intel Arria 10 User Manual page 338

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Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Added a note to the "Parameterizing the 1G/10GbE PHY" section.
• Added new signals to the "Control and Status Signals" table.
• Changed the description for calc_clk_1g in the "Clock and Reset Signals" table.
Made the following changes to the PCI Express (PIPE) section:
• Updated the "Rate Switch Change" figure in the Gen3 features section.
2015.11.02 Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section:
• Changed the title of "TX and RX FIFO" to "Standard PCS FIFO" in the Standard PCS Ports table.
• Updated the description and range for "Enable fast sync status reporting for deterministic Latency
SM" parameter in the Standard PCS Parameters table.
• Changed the title of "TX and RX FIFO Parameters" to "Standard PCS FIFO Parameters" in the
Standard PCS Parameters table.
• Updated the "Error marking type" range in the KR-FEC Parameters table in the Enhanced PCS
Parameters section.
• Updated the "Number of fixed DFE taps" value in the Equalization table in the PMA Parameters
section.
• Added a new parameter "Provide separate interface for each channel" in the General and Datapath
Options table in the General and Datapath Parameters section.
• Updated the "PMA configuration rules" value in the General and Datapath Options table in the
General and Datapath Parameters section.
• Removed footnote and added "Hard IP for PCI Express to Native PHY IP" in the "Arria 10 Transceiver
Protocols and PHY IP Support" table.
• Updated the description for "Enable tx_pma_ rxfound port (QPI)" parameter in the TX PMA Optional
Ports table in the PMA Parameters section.
• Updated the descriptions for "TX FIFO Mode","Enable tx_enh_fifo_full port", "Enable
tx_enh_fifo_empty port" parameters in the Enhanced PCS TX FIFO Parameters table in the
Enhanced PCS Parameters section.
• Updated the descriptions for "Enable rx_enh_fifo_full port", "Enable rx_enh_fifo_empty port"
parameters in the Enhanced PCS RX FIFO Parameters table in the Enhanced PCS Parameters
section.
• Updated the description for "Enable RX byte deserializer" parameter in the Byte Serializer and
Deserializer Parameters table in the Standard PCS Parameters section.
• Updated the description for "Share reconfiguration interface" parameter in the Dynamic
Reconfiguration table in the Dynamic Reconfiguration Parameters section.
• Updated the values and descriptions in the Configuration Profiles table in the Dynamic
Reconfiguration Parameters section.
• Updated the foot note for "tx_pma_clkout" clock to suggest what to do with the clock.
• Updated the description for "tx_dispval[<n>(<w>/<s>-1:0]" signal in the 8B/10B Encoder and
Decoder table in the Standard PCS Ports section.
• Updated the values and descriptions in the Configuration Profiles table in the Dynamic
Reconfiguration Parameters section.
• Updated the descriptions for "Enable tx_std_ pcfifo_full port", "Enable tx_std_ pcfifo_empty port",
"Enable rx_std_ pcfifo_full port", "Enable rx_std_ pcfifo_empty port" in the TX and RX FIFO
Parameters table in the Standard PCS Parameters section.
• Added links to other sections which describe the RX rate match FIFO in Basic, GBE and Transceiver
channel datapath modes in the Rate Match FIFO Parameters table in the Standard PCS Parameters
section.
• Updated value for Transceiver Configuration rules parameter in the " General and Datapath Options"
table in the General and Datapath Parameters section.
• Added a new parameter "Provide separate interface for each channel" in the " General and Datapath
Options" table in the General and Datapath Parameters section.
• Updated "Transceiver Native PHY IP Core Parameter Editor" figure.
• Updated "General, Common PMA Options, and Datapath Options" table.
• Added parameter "Enable tx_pma_analog_reset_ackport" in "TX PMA Optional Ports" table.
• Updated parameter "Number of fixed DFE taps" in "Equalization" table.
• Added parameter "Enable rx_analog_reset_ack port" in "RX PMA Optional Ports" table.
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Intel Arria 10 Transceiver PHY User Guide
338
2. Implementing Protocols in Arria 10 Transceivers
Changes
UG-01143 | 2018.06.15
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