Intel Arria 10 User Manual page 16

channels in the bank can be reconfigured as GX transceiver channels. However, when
any of the GT capable transceiver channels in transceiver banks GXBL1E, GXBL1G,
and GXBL1H is enabled as a GT transceiver channel, the remaining channels in the
transceiver bank cannot be used with the exception of the other GT capable channel in
the transceiver bank.
If you're using GT transceivers in bank GXBL1E, then the adjacent PCIe Hard IP block
cannot be used.
Figure 8. Arria 10 GT Device with 72 Transceiver Channels and Four PCIe Hard IP
Blocks
CH5 GX or Restricted
CH4 GT or GX
CH3 GT or GX
CH2 GX or Restricted
CH1
GX or Restricted
CH0
GX or Restricted
The GT device has 72 transceiver channels, which include 6 GT transceiver channels
supporting data rates greater than 17.4 Gbps. If all six GT transceiver channels are
used in GT mode, there are 54 GX transceiver channels that can drive chip to chip
data rates up to 17.4 Gbps and backplanes at data rates up to 12.5 Gbps and 12 GX
channels that are unusable.
In the GT device, the GX transceiver channels on the entire right side can be used in
standard or reduced power mode. In GT devices where none of the GT channels are
used to operate in GT data rates above 17.4 Gbps, the transceiver channels on either
the entire right side or entire left side can be used as GX channels in standard or
reduced power mode.
Related Information
• IntelArria 10 Avalon-ST Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
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Intel Arria 10 Transceiver PHY User Guide
16
CH5 GX or Restricted
GT Channels
CH4
GX or Restricted
Capable of Short
CH3
GX or Restricted
Reach 25.8 Gbps
CH2 GX or Restricted
CH1 GT or GX
CH0 GT or GX
Transceiver
Bank
Notes:
(1) Nomenclature of left column bottom transceiver banks always end with "C".
(2) Nomenclature of right column bottom transceiver banks may end with "C", "D", or "E".
(3) If a GT channel is used in transceiver bank GXBL1E, the PCIe Hard IP adjacent to GXBL1F and GXBL1E cannot be used.
Legend:
GT transceiver channels (channel 0, 1, 3, and 4).
GX transceiver channels (channel 2 and 5) with usage restrictions.
GX transceiver channels without usage restrictions.
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
®
1. Arria 10 Transceiver PHY Overview
GT 115 SF45
Transceiver Transceiver
GXBL1H
GT 090 SF45
Bank Bank
Transceiver Transceiver
GXBL1G
Bank Bank
Transceiver Transceiver
GXBL1F
PCIe
Bank Bank
Gen1 - Gen3 Gen1 - Gen3
Hard IP
GXBL1E
Transceiver Transceiver
Bank (3) Bank
GXBL1D Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen3
Gen1 - Gen3
Hard IP
(with CvP)
GXBL1C Transceiver Transceiver
(1)
Bank Bank
UG-01143 | 2018.06.15
Transceiver GXBR4H
Bank
Transceiver
GXBR4G
Bank
Transceiver
PCIe
GXBR4F
Bank
Hard IP
Transceiver GXBR4E
Bank
Transceiver GXBR4D
PCIe
Bank
Hard IP
Transceiver GXBR4C
(2)
Bank