Intel Arria 10 User Manual page 340

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• Added table "Parameters for Arria 10 ATX PLL IP in PIPE Gen1, Gen2, Gen3 modes" in the "ATX PLL
IP Parameter Settings for PIPE" section.
• Updated description of port pipe_tx_elecidle in the "Ports for Arria 10 Transceiver Native PHY in
PIPE Mode" table.
• Updated description of port pipe_tx_compliance in the "Ports for Arria 10 Transceiver Native PHY in
PIPE Mode" table.
• Updated description of port pipe_g3_txdeemph[17:0] in the "Ports for Arria 10 Transceiver Native
PHY in PIPE Mode" table.
• Added table "fPLL Ports for PIPE" in the section "fPLL Ports for PIPE" section.
• Added table" ATX PLL Ports for PIPE " in the "ATX PLL Ports for PIPE" section.
• Added table "Arria 10 Preset Mappings to TX De-emphasis" in the "Preset Mappings to TX De-
emphasis" section.
• Updated figure "Alternate Configuration" figure in the "How to Place Channels for PIPE
Configurations" section.
• Updated the "PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate" section.
Made the following changes to the Other Protocols section:
• Added the "Enhanced PCS FIFO Operation" section.
• Changed the minimum data rate from 960 Mbps to 1.0 Gbps in the "General and Datapath
Parameters" table.
2015.05.11 Made the following changes to the 10GBASE-KR PHY IP Core section:
• Changed the register definitions for word address 0x4D0 in the "10GBASE-KR PHY Register
Definitions" section.
Made the following changes to the 10GBASE-R section:
• Added a parameter to the "RX PMA Parameters" table.
Made the following changes to the 10GBASE-KR PHY IP Core section:
• Changed the following bits and descriptions in the "10GBASE-KR PHY Register Definitions" section:
— Changed the bit and description for address 0x4D0[21:20].
— Added address 0x4D0[22].
— Removed address 0x4D0[26:24].
— Added address 0x4D0[28:24].
— Removed addresses 0x4D0[27] and 0x4D0[28].
Made the following changes to the Interlaken section:
• Added available preset variations to the "Interlaken" and "How to Implement Interlaken in Arria 10
Transceivers" sections.
• Updated the values for some parameters in the "TX PMA Parameters", "RX PMA Parameters",
"Enhanced PCS Parameters", "Interlaken Frame Generator Parameters", and "Interlaken Frame
Synchronizer Parameters" tables.
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Changed the product ID in the "1G/10GbE Release Information" table.
• Changed the descriptions in the "Clock and Reset Signals" table.
• Removed the following bits from address 0x4D0 in the "Register Definitions" table:
— 19:18
— 26:24
— 27
Made the following changes to the PCI Express section:
• Updated the "Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations", "PIPE Gen1/Gen2/
Gen3 Configurations", "PCIe Reverse Parallel Loopback Mode Datapath", and "Signals and Ports of
Native PHY IP for PIPE" figures.
• Updated "Rate Switch" Gen3 features.
• Updated the "Enable simplified interface" and "Provide separate interface for each channel"
parameters in the "Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes" table.
• Updated the "PCS TX channel; bonding master" parameters in the table "Parameters for Arria 10
Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA" table.
• Updated the "Selected CDR reference clock frequency" parameter in the "Parameters for Arria 10
Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX PMA" table.
• Updated "How to place channels for PIPE configurations" section to include placement guidelines for
using Arria 10 PCIe Hard IP.
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Intel Arria 10 Transceiver PHY User Guide
340
2. Implementing Protocols in Arria 10 Transceivers
Changes
UG-01143 | 2018.06.15
continued...