Intel Arria 10 User Manual page 490

PCS-PMA Supported Word
Interface Aligner Modes
Width
Synchronous State
Machine
5.3.2.1.6. Word Aligner RX Bit Reversal Feature
The RX bit reversal feature reverses the order of the data received from the PMA. It is
performed at the output of the Word Aligner and is available even when the Word
Aligner is disabled. If the data received from the PMA is a 10-bit data width, the bit
reversal feature switches bit [0] with bit [9], bit [1] with bit [8], and so on. For
example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled,
changes the data to 1100100001.
5.3.2.1.7. Word Aligner RX Byte Reversal Feature
The RX byte reversal feature is available only when the PCS-PMA interface width is 16
bits or 20 bits. This feature reverses the order of the data received from the PMA. RX
byte reversal reverses the LSByte of the received data with its MSByte and vice versa.
If the data received is 20-bits, bits[0..9] are swapped with bits[10..20] so that the
resulting 20-bit data is [[10..20],[0..9]]. For example, if the 20-bit data is
11001100001000011111, the byte reversal feature changes the data to
10000111111100110000.
5.3.2.2. RX Polarity Inversion Feature
The RX polarity inversion feature inverts each bit of the data received from the PMA. If
the data received is a 10-bit data. Bit[0] content is inverted to its complement,
~bit[0], bit[1] is inverted to its complement, ~bit[1], bit[2] is inverted to its
complement, ~bit[2], and so on. For example, if the 10-bit data is 1111100000, the
polarity inversion feature inverts it to 0000011111.
® ®
Intel Arria 10 Transceiver PHY User Guide
490
Supported
rx_std_wa_patte
Word Aligner
behavior
rnalign
Pattern
Lengths
achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
7, 10, 20 FPGA fabric-driven
rx_std_wa_patt
signal
ernalign
has no effect on
word alignment.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
rx_syncstatus rx_patterndetect
behavior behavior
Stays high as long Asserted high for
as the one parallel clock
synchronization cycle when the word
conditions are alignment pattern
satisfied. appears in the
current word
boundary.