Intel Arria 10 User Manual page 105

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 39. Connection Guidelines for an Interlaken PHY Design
This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Intel
FPGA Wiki website.
For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic that is included in
the design example. The white blocks are your test logic or MAC layer logic.
9. Simulate your design to verify its functionality.
Figure 40. 24 Lanes Bonded Interlaken Link, TX Direction
To show more details, three different time segments are shown with the same zoom level.
tx_enh_frame_burst_en[0]
24 lanes bonded Interlaken link, TX direction
Reset
Controller
Control and Status
Pattern
Generator
Control and Status
Pattern
Verifier
tx_ready Pre-Fill
Asserted Stage
pll_locked
tx_analogreset
24`h000000
tx_clkout[0]
tx_clkout
tx_digitalreset
24`h000000
tx_ready[0]
tx_ready
24`... 24`hffffff
tx_enh_data_valid[0]
tx_enh_data_valid
24`h000000 24`hffffff
tx_enh_fifo_full
24`h000000
tx_enh_frame[0]
tx_enh_frame
24`h000000 24`h000000
tx_enh_frame_burst_en
24`hffffff 24`h000000
tx_parallel_data
1536`h0123456789abcdef01234567
tx_control
72`h249249249249249249
tx_enh_fifo_empty
24`hffffff 24`h000000
tx_enh_fifo_pempty
24`hffffff 24`h000000
PLL and CGB Reset
TX/RX Analog/Digital Reset
TX FIFO Status
TX Soft
TX FIFO Control
Bonding
TX Data Stream
RX FIFO Status
RX
Deskew
RX FIFO Control
RX Data Stream
Pre-Fill Completed
Assert burst_en for
All Lanes
24`h000000
24`h000000
24`hffffff
24`... 24`h000000
24`hffffff 24`hffffff
24`h000... 24`h000000
24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
Intel
PLL IP
TX Clocks
Arria 10
Transceiver
Native PHY
Send Data
Based on
FIFO Flags
24`h000000
24`h000000
24`hffffff
24`hffffff 24`h000000
24`h000000
24`hffffff 24`h000000
24`h000000
24`hffffff
1536`h0123456789abcdef01234567 1536`hbd212...
72`h249249249249249249
24`h000000
24`h000000
® ®
Arria 10 Transceiver PHY User Guide
105