Intel Arria 10 User Manual page 74

Name
tx_pma_qpipullup[<
n>-1:0]
tx_pma_qpipulldn[<
n>-1:0]
tx_pma_txdetectrx[
<n>-1:0]
tx_pma_rxfound[<n>
-1:0]
rx_seriallpbken[<n
>-1:0]
Table 46. RX PMA Ports
Name
rx_serial_data[<n>
-1:0]
rx_cdr_refclk0
–
rx_cdr_refclk1
rx_cdr_refclk4
rx_analog_reset_ac
k
rx_pma_clkout
rx_pma_div_clkout
® ®
Intel Arria 10 Transceiver PHY User Guide
74
Direction Clock Domain
Input Asynchronous
Input Asynchronous
Input Asynchronous
Output Synchronous to
rx_coreclkin
based
rx_clkout
on the
configuration.
Input Asynchronous
Direction Clock Domain
Input N/A
Input Clock
Optional Ports
Input Clock
Output Asynchronous
Output Clock
Output Clock
2. Implementing Protocols in Arria 10 Transceivers
Description
This port is available if you turn on Enable
tx_pma_qpipullup port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
This port is available if you turn on Enable
tx_pma_qpipulldn port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
This port is available if you turn on Enable
tx_pma_txdetectrx port (QPI) in the Transceiver Native
PHY IP core Parameter Editor. When asserted, the receiver
detect block in TX PMA detects the presence of a receiver at
the other end of the channel. After receiving the
request, the receiver detect block
tx_pma_txdetectrx
initiates the detection process. Use this port for Quick Path
Interconnect (QPI) applications only.
This port is available if you turn on Enable
tx_rxfound_pma port (QPI) in the Transceiver Native PHY
or
IP core Parameter Editor. When asserted, indicates that
the receiver detect block in TX PMA has detected a receiver
at the other end of the channel. Use this port for Quick Path
Interconnect (QPI) applications only.
This port is available if you turn on Enable rx_seriallpbken
port in the Transceiver Native PHY IP core Parameter
Editor. The assertion of this signal enables the TX to RX
serial loopback path within the transceiver. This signal can be
enabled in Duplex or Simplex mode. If enabled in Simplex
mode, you must drive the signal on both the TX and RX
instances from the same source. Otherwise the design fails
compilation.
Description
Specifies serial data input to the RX PMA.
Specifies reference clock input to the RX clock data recovery
(CDR) circuitry.
Specifies reference clock inputs to the RX clock data recovery
(CDR) circuitry.
Enables the optional rx_pma_analog_reset_ack output. This
port should not be used for register mode data transfers.
This clock is the recovered parallel clock from the RX CDR
circuitry.
The deserializer generates this clock. This is used to drive core
logic, PCS-to-FPGA fabric interface, or both. If you specify a
rx_pma_div_clkout division factor of 1 or 2, this clock output
is derived from the PMA parallel clock (low speed parallel
clock). If you specify a rx_pma_div_clkout division factor of
33, 40, or 66, this clock is derived from the PMA serial clock.
This clock is commonly used when the interface to the RX FIFO
runs at a different rate than the PMA parallel clock (low speed
parallel clock) frequency, such as 66:40 applications.
UG-01143 | 2018.06.15
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