Intel Arria 10 User Manual page 322

Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver
Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS
Interface width of 128 bits
rx_is_lockedtodata
5. Select Tools
PLL
on page 354 for detailed steps.
6. Configure the ATX PLL IP using the Parameter Editor.
• Select the GT clock output buffer.
• Enable the PLL GT clock output port.
• Set the PLL output clock frequency to the Native PHY IP recommended
frequency.
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Intel Arria 10 Transceiver PHY User Guide
322
tx_cal_busy
NIOS
rx_cal_busy Hard Calibration IP
TX PMA
tx_serial_data
Serializer
tx_serial_clk0
(from TX PLL)
RX PMA
Deserializer
rx_serial_data
CDR
rx_cdr_refclk0
rx_is_lockedtoref
refclk
IP Catalog
Arria 10 Transceiver ATX PLL. Refer to
2. Implementing Protocols in Arria 10 Transceivers
TX Enhanced PCS
tx_parallel_data[127:0]
tx_enh_data_valid
RX Enhanced PCS
rx_parallel_data[127:0]
Basic Functions Clocks
Instantiating the ATX PLL IP Core
UG-01143 | 2018.06.15
reconfig_reset
Reconfiguration
reconfig_clk
Registers
reconfig_avmm
tx_digital_reset tx_digital_reset
tx_control[17:0] tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin tx_coreclkin
tx_clkout tx_clkout
tx_enh_data_valid
tx_analog_reset
rx_analog_reset
rx_digital_reset rx_digital_reset
rx_clkout rx_clkout
rx_coreclkin rx_coreclkin
rx_parallel_data[127:0]
rx_control[19:0] rx_control[19:0]
PLLs and Resets