Intel Arria 10 User Manual page 482

5.3.1.2.2. Byte Serializer Disabled Mode
In disabled mode, the byte serializer is bypassed. The data from the TX FIFO is
directly transmitted to the 8B/10B encoder, TX Bitslip, or Serializer, depending on
whether or not the 8B/10B encoder and TX Bitslip are enabled. Disabled mode is used
in low speed applications such as GigE, where the FPGA fabric and the TX standard
PCS can operate at the same clock rate.
5.3.1.2.3. Byte Serializer Serialize x2 Mode
The serialize x2 mode is used in high-speed applications such as the PCIe Gen1 or
Gen2 protocol implementation, where the FPGA fabric cannot operate as fast as the TX
PCS.
In serialize x2 mode, the byte serializer serializes 16-bit, 20-bit (when 8B/10B
encoder is not enabled), 32-bit, and 40-bit (when 8B/10B encoder is not enabled)
input data into 8-bit, 10-bit, 16-bit, and 20-bit data, respectively. As the parallel data
width from the TX FIFO is halved, the clock rate is doubled.
After byte serialization, the byte serializer forwards the least significant word first
followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards
followed by
Related Information
PCI Express (PIPE)
For more information about using the Serialize x2 mode in the PCIe protocol.
5.3.1.2.4. Byte Serializer Serialize x4 Mode
The serialize x4 mode is used in high-speed applications such as the PCIe Gen3
protocol mode, where the FPGA fabric cannot operate as fast as the TX PCS.
In serialize x4 mode, the byte serializer serializes 32-bit data into 8-bit data. As the
parallel data width from the TX FIFO is divided four times, the clock rate is
quadrupled.
After byte serialization, the byte serializer forwards the least significant word first
followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards
followed by
tx_parallel_data[31:24]
Related Information
PCI Express (PIPE)
For more information about using the Serialize x4 mode in the PCIe protocol.
5.3.1.3. 8B/10B Encoder
The 8B/10B encoder takes in 8-bit data and 1-bit control as input and converts them
into a 10-bit output. The 8B/10B encoder automatically performs running disparity
check for the 10-bit output. Additionally, the 8B/10B encoder can control the running
disparity manually using the
® ®
Intel Arria 10 Transceiver PHY User Guide
482
tx_parallel_data[31:16]
on page 229
tx_parallel_data[15:8]
.
on page 229
tx_forcedisp
5. Arria 10 Transceiver PHY Architecture
tx_parallel_data[15:0]
.
tx_parallel_data[7:0]
,
tx_parallel_data[23:16]
and ports.
tx_dispval
UG-01143 | 2018.06.15
first,
first,
and