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Document
Version
•
Re-organized the chapter outline to better match the reconfiguration flow.
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Updated the introduction section of the chapter to better explain dynamic reconfiguration use cases.
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Added figures Reconfiguration Interface in Arria 10 Transceiver IP Cores and Top Level Signals of
the Reconfiguration Interface.
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Added Timing Closure Recommendations section.
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Changed Max Vod Value in Table: PMA Analog Feature Offsets.
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Updated Table: Valid Maximum Pre-Emphasis Settings.
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Updated the Ports and Parameters section:
— Updated the description to better indicate the difference between "Shared" and "Not Shared"
— Updated Avalon clock frequency to 100 MHz.
— Updated the signal names in Table: Reconfiguration Interface Ports with Shared Reconfiguration
•
Added a description in Interfacing with Reconfiguration Interface section to indicate the steps to
request access of the Avalon-MM interface.
•
Updated steps in Performing a Read to the Reconfiguration Interface and Performing a Write to the
Reconfiguration Interface sections.
•
Updated Using Configuration Files section to with a detailed description of when to use configuration
files.
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Updated the steps in Switching Transmitter PLL, Switching Reference Clocks, and Changing PMA
Analog Parameters sections.
2014.10.08
Made the following changes:
•
Minor editorial changes. Corrected typographical errors in Ports and Parameters and Native PHY IP
Core Embedded Debug sections.
•
Corrected an error in "Example 6-1: Steps to Merge Transceiver Channels" in Document Channel
Merging Requirements section.
2014.08.15
Made the following changes:
•
Updated MegaWizard references to IP Catalog or Parameter Editor.
•
Updated table "Avalon Interface Parameters"
— Added description for Altera Debug Master Endpoint.
— Added Embedded Debug Parameters.
•
Corrected typos and updated values in table "PMA Analog Feature Offsets".
•
Added a new table "Valid Maximum Pre-Emphasis Settings" in Changing Analog Parameters Section.
•
Updated the description for 0xB reconfiguration address bit[7:5] in table "PRBS Checker Offsets".
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Updated the Unsupported Features section and removed some unsupported features.
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Changed the name of Transceiver and PLL Address Map to Arria 10 Transceiver Register Map.
Updated the description to better explain the scope of the register map.
•
Added a new section for Embedded Debug feature.
2013.12.02
Initial release.
®
®
Intel
Arria
10 Transceiver PHY User Guide
566
reconfiguration interface.
Interface Enabled and Reconfiguration Interface Ports with Shared Reconfiguration Interface
Disabled.
6. Reconfiguration Interface and Dynamic Reconfiguration
Changes
UG-01143 | 2018.06.15
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