Intel Arria 10 User Manual page 218

Transmitter and Receiver State Machines
In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver
state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008
specification.
The transmitter state machine performs the following functions in conformance with
the 10GBASE-X PCS:
• Encoding the XGMII data to PCS code groups
• Converting Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R||
ordered sets
The receiver state machine performs the following functions in conformance with the
10GBASE-X PCS:
• Decoding the PCS code groups to XGMII data
• Converting Sync ||K||, Align ||A||, and Skip ||R|| ordered sets into Idle ||I||
ordered sets
Synchronization
The word aligner block in the receiver PCS of each of the four XAUI lanes implements
the receiver synchronization state diagram shown in Figure 48-7 of the
IEEE802.3-2008 specification.
The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner
is synchronized to a valid word boundary.
Deskew
The lane aligner block in the receiver PCS implements the receiver deskew state
diagram shown in Figure 48-8 of the IEEE 802.3-2008 specification.
The lane aligner starts the deskew process only after the word aligner block in each of
the four XAUI lanes indicates successful synchronization to a valid word boundary.
The XAUI PHY IP core provides a status signal to indicate successful lane deskew in
the receiver PCS.
Clock Compensation
The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm
difference between the remote transmitter and the local receiver. It compensates by
inserting and deleting Skip ||R|| columns, depending on the ppm difference.
The clock compensation operation begins after:
• The word aligner in all four XAUI lanes indicates successful synchronization to a
valid word boundary.
• The lane aligner indicates a successful lane deskew.
The rate match FIFO provides status signals to indicate the insertion and deletion of
the Skip ||R|| column for clock rate compensation.
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Intel Arria 10 Transceiver PHY User Guide
218
2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15