Intel Arria 10 User Manual page 238

The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows:
1. The PHY-MAC layer implemented in FPGA fabric requests a rate change through
pipe_rate[1:0]
2. The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts
the PCS reset.
3. The ASN asserts the clock shutdown signal to the Standard PCS and Gen3 PCS to
dynamically shut down the clock.
4. When the rate changes to or from the Gen3 speed, the ASN asserts the clock and
data multiplexer selection signals.
5. The ASN uses a
the PMA.
6. The ASN continuously monitors the
PMA.
7. After the ASN receives the
shut down signals to release the clock.
8. The ASN deasserts the PCS reset.
9. The ASN sends the speed change completion to the PHY-MAC interface. This is
done through the
Figure 98. Speed Change Sequence
pipe_tx_elecidle
pipe_rate[1:0]
pipe_sw[1:0]
pipe_sw_done[1:0]
pipe_phy_status
2.7.2.2.3. Gen3 Transmitter Electrical Idle Generation
In the PIPE 3.0-based interface, you can place the transmitter in electrical idle during
low power states. Before the transmitter enters electrical idle, you must send the
Electrical Idle ordered set, consisting of 16 symbols with value 0x66. During electrical
idle, the transmitter differential and common mode voltage levels are based on the
PCIe Base Specification 3.0.
2.7.2.2.4. Gen3 Clock Compensation
Enable this mode from the Parameter Editor when using the Gen3 PIPE transceiver
configuration rule.
To accommodate PCIe protocol requirements and to compensate for clock frequency
differences of up to ±300 ppm between source and termination equipment, receiver
channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP
characters (32 bits) to keep the FIFO from becoming empty or full. If the rate match
FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is
nearly empty, the FIFO inserts a SKP character at the start of the next available SKP
ordered set. The
and deletion.
® ®
Intel Arria 10 Transceiver PHY User Guide
238
.
output signal to send a rate change request to
pipe_sw[1:0]
pipe_sw_done[1:0]
pipe_sw_done[1:0]
pipe_phy_status
00 10
00 10
00 10
pipe_rx_status [2:0]
2. Implementing Protocols in Arria 10 Transceivers
input signal from the
signal, it deasserts the clock
signal to PHY-MAC interface.
signal indicates FIFO full, empty, insertion
UG-01143 | 2018.06.15