Intel Arria 10 User Manual page 487

5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
The
rx_syncstatus
datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after
asserted, both
parallel clock cycle. Any word alignment pattern received thereafter in the same word
boundary causes only
alignment pattern received thereafter in a different word boundary causes the word
aligner to re-align to the new word boundary only if
asserted. The word aligner asserts
whenever it re-aligns to the new word boundary.
5.3.2.1.3. Word Aligner Synchronous State Machine Mode
In synchronous state machine mode, when the programmed number of valid
synchronization code groups or ordered sets is received,
high to indicate that synchronization is acquired. The
constantly driven high until the programmed number of erroneous code groups is
received without receiving intermediate good groups, after which
driven low.
The word aligner indicates loss of synchronization (
until the programmed number of valid synchronization code groups are received
again.
5.3.2.1.4. Word Aligner Deterministic Latency Mode
In deterministic latency mode, the state machine removes the bit level latency
uncertainty. The deserializer of the PMA creates the bit level latency uncertainty as it
comes out of reset.
The PCS performs pattern detection on the incoming data from the PMA. The PCS
aligns the data, after it indicates to the PMA the number of serial bits to clock slip the
boundary.
If the incoming data has to be realigned,
reasserted to initiate another pattern alignment. Asserting
rx_std_wa_patternalign
already achieved. This may cause
Table 260. PCS-PMA Interface Widths and Protocol Implementations
PCS-PMA Interface Width
8
10
16
20
and
rx_patterndetect
and
rx_syncstatus rx_patterndetect
rx_patterndetect
rx_syncstatus
can cause the word align to lose synchronization if
rx_syncstatus
signals, with the same latency as the
rx_std_wa_patternalign
are driven high for one
to go high for one clock cycle. Any word
rx_std_wa_patternalign
for one parallel clock cycle
rx_syncstatus
rx_syncstatus
rx_syncstatus
rx_std_wa_patternalign
to go low.
Protocol Implementations
Basic
• Basic
• Basic rate match
• CPRI
• PCIe Gen1 and Gen2
• GigE
Basic
• CPRI
• Basic
• Basic rate match
® ®
Intel Arria
is
is
is driven
signal is
is
rx_syncstatus
remains low)
must be
10 Transceiver PHY User Guide
487