Intel Arria 10 User Manual page 162

Address Bit
0x464 0
0x465 0
0x466 0
0x467 0
2.6.3.7. Creating a 10GBASE-KR Design
Follow these steps to create a 10GBASE-KR design.
1. Generate the 10GBASE-KR PHY with the required parameterization.
The 10GBASE-KR PHY IP core includes a reconfiguration block. The reconfiguration
block provides the Avalon-MM interface to access the PHY registers.
2. Instantiate a reset controller. You can generate a Transceiver Reset Controller IP
core from the IP Catalog. You must connect the Transceiver Reset Controller IP
core and 10GBASE-KR PHY IP core power and reset signals.
3. Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 10GBASE-KR
PHY and TX PLLs. For the 1G data rate you can use either fPLL, ATX PLL, or CMU
PLL. For the 10G data rate you can use ATX PLL or CMU PLL.
4. Generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference
clock.
5. Use the
the 156.25 MHz XGMII clock from the 10G reference clock.
Unlike in the 10GBASE-KR PHY IP core for Stratix V devices, no Memory
Initialization Files (.mif) are required for the 10GBASE-KR design in Arria 10
devices.
6. Complete the design by creating a top level module to connect all the IP
(10GBASE-KR PHY IP core, PLL IP core, and Reset Controller) blocks.
Related Information
• fPLL
• CMU PLL
• ATX PLL
• Using the Transceiver PHY Reset Controller
• 10GBASE-KR Functional Description
® ®
Intel Arria 10 Transceiver PHY User Guide
162
R/W Name
RW
pma_rx_set_locktoda
ta
RW
pma_rx_set_locktore
f
RO
pma_rx_is_lockedtod
ata
RO
pma_rx_is_lockedtor
ef
from the 10GBASE-KR PHY or generate a fPLL to create
tx_pma_divclk
on page 359
on page 368
on page 350
2. Implementing Protocols in Arria 10 Transceivers
Description
When set, programs the RX clock data recovery (CDR) PLL
to lock to the incoming data.
When set, programs the RX CDR PLL to lock to the reference
clock.
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode.
When asserted, indicates that the RX CDR PLL is locked to
the reference clock.
on page 433
on page 136
UG-01143 | 2018.06.15