Intel Arria 10 User Manual page 79

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Name
rx_coreclkin
rx_clkout
Table 51. Enhanced PCS TX FIFO
Name
tx_enh_data_valid[<n>-
1:0]
tx_enh_fifo_full[<n>-1
:0]
tx_enh_fifo_pfull[<n>-
1:0]
tx_enh_fifo_empty[<n>-
1:0]
tx_enh_fifo_pempty[<n>
-1:0]
Table 52. Enhanced PCS RX FIFO
Name
rx_enh_data_valid[<n>
-1:0]
Direction Clock Domain
(
rx_coreclk
or
in
)
rx_clkout
Input Clock
Output Clock
Direction Clock Domain
Input Synchronous to
the clock driving
the write side of
the FIFO
(
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
(
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or
tx_clkout
Output Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or
tx_clkout
Direction Clock Domain
Output Synchronous to
the clock driving
the read side of
Description
The FPGA fabric clock. Drives the read side of the RX FIFO. For
Interlaken protocol, the frequency of this clock could be from
datarate/67 to datarate/32.
The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Enhanced PCS. The
frequency of this clock is equal to data rate divided by
PCS/PMA interface width.
Description
Assertion of this signal indicates that the TX data is valid.
Connect this signal to 1'b1 for 10GBASE-R without 1588.
For 10GBASE-R with 1588, you must control this signal
based on the gearbox ratio. For Basic and Interlaken, you
need to control this port based on TX FIFO flags so that
the FIFO does not underflow or overflow.
)
Refer to Enhanced PCS FIFO Operation
more details.
Assertion of this signal indicates the TX FIFO is full.
Because the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
)
This signal gets asserted when the TX FIFO reaches its
partially full threshold. Because the depth is always
constant, you can ignore this signal for the phase
compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
When asserted, indicates that the TX FIFO is empty. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
When asserted, indicates that the TX FIFO has reached its
specified partially empty threshold. When you turn this
option on, the Enhanced PCS enables the
port, which is asynchronous. This
tx_enh_fifo_pempty
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation
more details.
Description
When asserted, indicates that
valid. Discard invalid RX parallel data
when
rx_enh_data_valid
®
Intel Arria
on page 297 for
on page 297 for
on page 297 for
on page 297 for
on page 297 for
is
rx_parallel_data
signal is low.
continued...
®
10 Transceiver PHY User Guide
79