Intel Arria 10 User Manual page 312

Note:
The
rx_parallel_data
bit reversal features being disabled.
Figure 153. TX Bit Slip in 8-bit Mode
tx_parallel_data
tx_std_bitslipboundarysel
Figure 154. TX Bit Slip in 10-bit Mode
tx_parallel_data
tx_std_bitslipboundarysel
Figure 155. TX Bit Slip in 16-bit Mode
tx_parallel_data
tx_std_bitslipboundarysel
Figure 156. TX Bit Slip in 20-bit Mode
tx_parallel_data
tx_std_bitslipboundarysel
2.9.2.13. TX Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be
swapped during board layout. Solutions such as a board respin or major updates to
the PLD logic can be expensive. The transmitter polarity inversion feature is provided
to correct this situation.
Transmitter polarity inversion can be enabled in low latency, basic, and basic rate
match modes.
To enable TX polarity inversion, select the Enable tx_polinv port option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic
reconfiguration.
This mode adds
tx_polinv
is asserted, the TX data transmitted has a reverse polarity.
® ®
Intel Arria 10 Transceiver PHY User Guide
312
values in the following figures are based on the TX and RX
= 8'hbc.
tx_std_bitslipboundarysel
00001
tx_parallel_data bc
rx_parallel_data 79
= 10'h3bc.
tx_std_bitslipboundarysel
00011
tx_parallel_data 3bc
rx_parallel_data 1e7
= 16'hfcbc.
tx_std_bitslipboundarysel
00011
tx_parallel_data fcbc
rx_parallel_data 5e7f
= 20'hF3CBC.
tx_std_bitslipboundarysel
00111
tx_parallel_data f3cbc
rx_parallel_data e5e1f
. If there is more than one channel in the design,
tx_polinv
is a bus with each bit corresponding to a channel. As long as
2. Implementing Protocols in Arria 10 Transceivers
= 5'b00001 (bit slip by 1 bit).
= 5'b00011 (bit slip by 3 bits).
=5'b00011 (bit slip by 3 bits).
= 5'b00111 (bit slip by 7 bits).
UG-01143 | 2018.06.15
tx_polinv