Intel Arria 10 User Manual page 316

TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_seriallpbken port
Table 219. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
® ®
Intel Arria 10 Transceiver PHY User Guide
316
Parameter
Parameter
2. Implementing Protocols in Arria 10 Transceivers
Range
1, 2, 4, 8
1, 2, 3, 4
0 (Depends on the Number of TX PLL clock
inputs per channel value)
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Range
1, 2, 3, 4, 5
0, 1, 2, 3, 4
Legal range defined by Quartus Prime software
100, 300, 500, 1000
manual
disabled
On/Off
On/Off
Disabled, 1, 2, 33, 40, 50, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
UG-01143 | 2018.06.15
3, 7