Intel Arria 10 User Manual page 404

3.11.2.1. Implementing x6/xN Bonding Mode
Figure 194. PHY IP Core and PLL IP Core Connection for x6/xN Bonding Mode
Steps to implement a x6/xN bonded configuration
1. You can instantiate either the ATX PLL or the fPLL for x6/xN bonded configuration.
• Refer to
fPLL IP Core
drive the Master CGB, only the ATX PLL or fPLL can be used for bonded
configurations.
2. Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block and Enable bonding clock output ports.
3. Configure the Native PHY IP core using the IP Parameter Editor .
• Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding .
• Set the number of channels required by your design. In this example, the
number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core.
® ®
Intel Arria 10 Transceiver PHY User Guide
404
Transceiver PLL
Instance (5 GHz)
x1 x6
ATX PLL Master
CGB
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
Instantiating the ATX PLL IP Core
on page 362 for detailed steps. Because the CMU PLL cannot
3. PLLs and Clock Networks
Native PHY Instance
(10 CH x6/xN Bonding 10 Gbps)
x6
TX Channel
x6
TX Channel
x6
TX Channel
x6
TX Channel
x6
TX Channel
x6
TX Channel
xN
TX Channel
xN
TX Channel
xN
TX Channel
xN
TX Channel
on page 354 or
UG-01143 | 2018.06.15
Instantiating the