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The Backplane Ethernet 10GBASE-KR PHY IP core includes the following new modules
to enable operation over a backplane:
•
Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to
automatically configure the link-partner TX PMDs for the lowest Bit Error Rate
(BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
•
Auto negotiation (AN)—The 10GBASE-KR PHY IP core can auto-negotiate between
1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is
mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std
802.3ap-2007.
•
Forward Error Correction (FEC)—FEC function is an optional feature defined in
Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction
mechanism.
Related Information
•
IEEE Std 802.3ap-2008 Standard
•
Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems
2.6.3.1. 10GBASE-KR PHY Release Information
Table 106.
10GBASE-KR PHY Release Information
Version
Release Date
Ordering Codes
Product ID
Vendor ID
2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the IP.
The following table shows the typical expected resource utilization for selected
configurations using the Quartus Prime software v15.1 for Arria 10 devices. The
numbers of ALMs and logic registers are rounded up to the nearest 100.
Table 107.
10GBASE-KR PHY Performance and Resource Utilization
Variant
10GBASE-KR PHY
10GBASE-KR PHY with FEC
2.6.3.3. 10GBASE-KR Functional Description
The following figure shows the supporting components inside the 10GBASE-KR PHY IP
core.
®
®
Intel
Arria
10 Transceiver PHY User Guide
136
Item
ALMs
2400
2400
2. Implementing Protocols in Arria 10 Transceivers
Description
16.0
May 2016
IP-10GBASEKRPHY (IP)
IPR-10GBASEKRPHY (Renewal)
0106
6AF7
ALUTs
Registers
3750
3100
3750
3100
UG-01143 | 2018.06.15
M20K
1
1
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