Intel Arria 10 User Manual page 144

Signal Name
tx_pma_clkout
rx_pma_clkout
tx_clkout
rx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
Related Information
• Input Reference Clock Sources
• PLLs
2.6.3.5.2. Data Interfaces
Table 115. XGMII Signals
The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the
MAC.
Signal Name
Input
xgmii_tx_dc[71:0
]
Input
xgmii_tx_clk
® ®
Intel Arria 10 Transceiver PHY User Guide
144
Direction
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
on page 349
Direction Clock Domain
10GbE XGMII Data Interface
Synchronous to
xgmii_tx_clk
Clock signal
2. Implementing Protocols in Arria 10 Transceivers
Description
Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
XGMII/GMII TX clock for the TX parallel data source interface. This
clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with
FEC enabled.
XGMII RX clock for the RX parallel data source interface. This clock
frequency is 257.81 in 10G mode, and 161.13 MHz with FEC
enabled.
The divided 33 clock from the TX serializer. You can use this clock for
the for or
xgmii_tx_clk xgmii_rx_clk
MHz for 10G. The frequencies are the same whether or not you
enable FEC.
The divided 33 clock from CDR recovered clock. The frequency is
156.25 MHz for 10G. The frequencies are the same whether or not
you enable FEC. This clock is not used for clocking the 10G RX
datapath.
Resets the analog TX portion of the transceiver PHY. Synchronous to
.
mgmt_clk
Resets the digital TX portion of the transceiver PHY. Synchronous to
.
mgmt_clk
Resets the analog RX portion of the transceiver PHY. Synchronous to
.
mgmt_clk
Resets the digital RX portion of the transceiver PHY. Synchronous to
.
mgmt_clk
Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
.
mgmt_clk
on page 372
XGMII data and control for 8 lanes. Each lane consists of 8
bits of data and 1 bit of control.
Clock for single data rate (SDR) XGMII TX interface to the
MAC. It should connect to
connected to the
tx_div_clkout
UG-01143 | 2018.06.15
. The frequency is 156.25
Description
. This clock can be
xgmii_rx_clk
; however, Intel
continued...