Intel Arria 10 User Manual page 88

Table 70. Standard PCS FIFO
Name
tx_std_pcfifo_full[<n
>-1:0]
tx_std_pcfifo_empty[<
n>-1:0]
rx_std_pcfifo_full[<n
>-1:0]
rx_std_pcfifo_empty[<
n>-1:0]
Table 71. Rate Match FIFO
Name
rx_std_rmfifo_full[<n
>-1:0]
rx_std_rmfifo_empty[<
n>-1:0]
rx_rmfifostatus[<n>-1
:0]
® ®
Intel Arria 10 Transceiver PHY User Guide
88
Direction Clock Domain
Output Synchronous
to the clock
driving the
write side of
the FIFO
(
tx_coreclki
or
n
)
tx_clkout
Output Synchronous
to the clock
driving the
write side of
the FIFO
(
tx_coreclki
or
n
)
tx_clkout
Output Synchronous
to the clock
driving the
read side of
the FIFO
(
rx_coreclki
or
n
)
rx_clkout
Output Synchronous
to the clock
driving the
read side of
the FIFO
(
rx_coreclki
or
n
)
rx_clkout
Direction Clock Domain
Output Asynchronous
Output Asynchronous
Output Asynchronous
2. Implementing Protocols in Arria 10 Transceivers
Description
Indicates when the standard TX FIFO is full.
Indicates when the standard TX FIFO is empty.
Indicates when the standard RX FIFO is full.
Indicates when the standard RX FIFO is empty.
Description
Rate match FIFO full flag. When asserted the rate match
FIFO is full. You must synchronize this signal. This port is
only used for GigE mode.
Rate match FIFO empty flag. When asserted, match FIFO is
empty. You must synchronize this signal. This port is only
used for GigE mode.
Indicates FIFO status. The following encodings are defined:
• 2'b00: Normal operation
•
2'b01: Deletion,
rx_std_rmfifo_full = 1
• 2'b10: Insertion,
rx_std_rmfifo_empty = 1
•
2'b11: Full.
rx_rmfifostatus
.
rx_parallel_data rx_rmfifostatus
to
rx_parallel_data[14:13]
UG-01143 | 2018.06.15
is a part of
corresponds
.