Intel Arria 10 User Manual page 488

5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes
Table 261. Word Aligner Pattern Length for Various Word Aligner Modes
PCS-PMA Supported Word
Interface Aligner Modes
Width
8 Bit slip
Manual
10 Bit slip
Manual
Deterministic latency
(CPRI mode only)
Synchronous State
Machine
® ®
Intel Arria 10 Transceiver PHY User Guide
488
Supported
rx_std_wa_patte
Word Aligner
behavior
rnalign
Pattern
Lengths
8
rx_std_wa_patt
has no
ernalign
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
8, 16 Word alignment is
controlled by
rx_std_wa_patt
and is
ernalign
edge-sensitive to
this signal.
7
rx_std_wa_patt
has no
ernalign
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
7, 10 Word alignment is
controlled by
rx_std_wa_patt
and is
ernalign
level-sensitive to
this signal.
10 Word alignment is
controlled by
rx_std_wa_patt
(edge-
ernalign
sensitive to this
signal) and the
state machine
works in
conjunction with
PMA to achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
7, 10
rx_std_wa_patt
n has no
ernalig
effect on word
alignment.
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
rx_syncstatus rx_patterndetect
behavior behavior
N/A N/A
Asserted high for Asserted high for
one parallel clock one parallel clock
cycle when the cycle when the word
word aligner aligns alignment pattern
to a new boundary. appears in the
current word
boundary.
N/A N/A
Asserted high for Asserted high for
one parallel clock one parallel clock
cycle when the cycle when the word
word aligner aligns alignment pattern
to a new boundary. appears in the
current word
boundary.
— —
Stays high as long Asserted high for
as the one parallel clock
synchronization cycle when the word
conditions are alignment pattern
satisfied.
continued...