Intel Arria 10 User Manual page 13

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1. Arria 10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Figure 4. Arria 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP
Blocks
GXBL1H
GXBL1G
GXBL1F
GXBL1E
GXBL1D
GXBL1C
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with "C".
(2) Nomenclature of right column bottom transceiver banks may end with "C", "D", or "E".
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 66 transceiver channels and three PCIe Hard IP blocks.
GX 115 RF40
Transceiver Transceiver GX 090 RF40
Bank Bank
Transceiver Transceiver
Bank Bank
Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen3
Hard IP
Transceiver Transceiver
Bank Bank
Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver Transceiver
(1) Bank Bank
Transceiver GXBR4J
Bank
Transceiver GXBR4I
Bank
Transceiver GXBR4H
Bank
Transceiver GXBR4G
Bank
Transceiver GXBR4F
PCIe
Bank
Gen1 - Gen3
Hard IP
Transceiver GXBR4E
Bank
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Intel Arria
CH2
Transceiver
CH1
Bank
CH0
CH5
CH4
CH3
Transceiver
CH2
Bank
CH1
CH0
(2)
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10 Transceiver PHY User Guide
13