Intel Arria 10 User Manual page 293

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 125. Connection Guidelines for a Basic with KR FEC Transceiver Design
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Enhanced PCS Architecture
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture
For more information about PMA architecture
• Using PLLs and Clock Networks
For more information about implementing PLLs and clocks
• PLLs
PLL architecture and implementation details
• Resetting Transceiver Channels
Reset controller general information and implementation details
• Enhanced PCS Ports
For detailed information about the available ports in the Basic protocol.
2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic
with KR FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 211. General and Datapath Parameters
The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and
datapath options to customize the transceiver.
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Design
Testbench
on page 447
on page 349
on page 76
Parameter
PLL IP Core
64d + 2c
Arria 10 Transceiver
Native PHY
on page 461
on page 398
on page 416
error, warning
Basic (Enhanced PCS), Basic w/KR FEC
Basic, QPI, GPON
TX / RX Duplex, TX Simplex, RX Simplex
1 to 96
GX transceiver channel: 1 Gbps
Intel
Reset
Controller
Range
(48)
to 17.4 Gbps
continued...
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Arria 10 Transceiver PHY User Guide
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