Intel Arria 10 User Manual page 128

Figure 58. Clock Generation and Distribution for 10GBASE-R with FEC Support
Example using a 64-bit PCS-PMA interface width.
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R
The XGMII interface, specified by IEEE 802.3-2008, defines the 32-bit data and 4-bit
wide control character. These characters are clocked between the MAC/RS and the PCS
at both the positive and negative edge (double data rate – DDR) of the 156.25 MHz
interface clock.
The transceivers do not support the XGMII interface to the MAC/RS as defined in the
IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control
single data rate (SDR) interface between the MAC/RS and the PCS.
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Intel Arria 10 Transceiver PHY User Guide
128
10GBASE-R Hard IP Transceiver Channel
TX
64 Bit Data
8 Bit Control
TX PCS
RX
64 Bit Data
8 Bit Control
RX PCS
156.25 MHz
rx_coreclkin
fPLL
8/33
2. Implementing Protocols in Arria 10 Transceivers
64
TX PMA
TX PLL
161.13 MHz
64
RX PMA
161.13 MHz
UG-01143 | 2018.06.15
10.3125 Gbps
Serial
pll_ref_clk
644.53125 MHz
10.3125 Gbps
Serial