Intel Arria 10 User Manual page 220

2.6.6.5. Transceiver Clocking and Channel Placement Guidelines in XAUI
Configuration
Transceiver Clocking
Figure 85. Transceiver Clocking for XAUI Configuration Without Phase Compensation
FIFO Enabled
The external ATX PLL generates the transmitter serial and parallel clocks for the four XAUI channels. You must
instantiate the PLL and connect it to XAUI. The x6 clock line carries the transmitter serial and parallel clocks to
the PMA and PCS of each of the four channels.
XAUI PHY IP Core
xgmii_tx_clk
xgmii_rx_clk
Note:
1. Use the ATX PLL as the transmit PLL for XAUI support in Arria 10 devices.
Note: When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver
channel. This ensures that the serial clock is running at 3.125 Gbps while the input
reference clock is 156.25 MHz.
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Intel Arria 10 Transceiver PHY User Guide
220
Channel 3 Soft PCS
Soft PCS
Channel 2
Channel 1
Soft PCS
Channel 0
Soft PCS
16 20
16
20 20
Parallel Clock
Parallel Clock
(Recovered) from Channel 0
(1)
ATX PLL
Serial Clock
(From the ×1 Clock Lines)
2. Implementing Protocols in Arria 10 Transceivers
Transmitter Standard PCS
Channel 3
Channel 2 Transmitter Standard PCS
Channel 1 Transmitter Standard PCS
Channel 0 Transmitter Standard PCS
20 10
Parallel Clock
/2
Receiver Standard PCS
20 10
/2
Parallel Clock (Recovered)
Master Clock Generation Block
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
UG-01143 | 2018.06.15
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter PMA Ch 1
Transmitter PMA Ch 0
Receiver PMA
10
Parallel Clock
Serial Clock
Parallel and Serial Clocks